1. Field of the Invention
The present invention relates to a mixed-signal control apparatus.
2. Description of Related Art
Generally, normal electronic products often employ modulation systems for modulating some controlled variables X (e.g., voltage, current, frequency, oscillation amplitude, phase, and pulse width). For example, a DC-DC converter is a typical one of the modulation systems. The DC-DC converter is adapted to modulate an input voltage into an output voltage Vo with a rated level. An analog control apparatus is capable of precisely controlling the modulation system to the specified controlled variable X. In principle, the controlled variable X in an analog control mode can be modulated to achieve any desired level despite affections by a loop gain, a thermal effect, and noises.
Correspondingly, in accordance with a digital control technology for a modulation system, a mixed-signal control apparatus is often employed for controlling the modulation system. The mixed-signal control apparatus employs a quantizing element to convert a controlled variable X of an analog domain outputted from the modulation system into a discrete domain, so as to control/calculate the controlled variable X with digital techniques, thus generating a digital control signal. Finally, another quantizing element converts the digital control signal back to a control signal of the analog domain, so as to control the modulation system to the specified controlled variable X.
Using a conventional mixed-signal control apparatus may disadvantageously cause affections including limit cycle, and process voltage temperature (PVT) variation. Generally, in order to reduce power consumption, delay cells are frequently employed in designing the architecture of the mixed-signal control apparatus. However, the said architecture does not include any precise reference circuit or regulation circuit, thus seriously suffering the affection of the PVT variation.
In terms of digital controlling, the limit cycle is actually caused by the discrete and finite setting points set by the quantizing element. The quantizing element hereby means an analog-to-digital converter (ADC) unit and a digital-to-analog converter (DAC). The limit cycle, which is a phenomenon of voltage jumping, is often caused by unmatched resolutions between the ADC unit and the DAC unit. Generally, the so-called resolution hereby is determined in accordance with the number of the setting points. For example, in a binary control system, an n-bit control character can generate 2n setting point statuses, which is used for representing the resolution of the binary control system. Taking a switching power system as an example, when a pulse width is modulated by 2n data (resolution), a quantization step thereof can be represented by VIN/2n.
If the resolution of the DAC unit is lower than the resolution of the ADC unit, a least significant bit (LSB) of the ADC unit will remain varying, because the output voltage modulated by the DAC unit fails to match the resolution of the ADC unit. As such, the system cannot latch up the output voltage, so that the phenomenon of output voltage jumping, which is known as the limit cycle, occurs. As shown in FIG. 1, a quantization step of the ADC unit is qADC, and a quantization step of the DAC unit is qDAC. The controlled variable (e.g., an output voltage Vo) outputted from the modulation system controlled by the DAC unit fails to match the resolution of the DAC unit, thus remaining varying. Therefore, the system is incapable of latching up the output voltage Vo, thus generating the voltage jumping phenomenon.
The limit cycle is a common problem which occurs in all mixed-signal circuits including feedback control (circuits including analog signals and digital signals at the same time). A conventional solution to the limit cycle is to utilize a relative large quantization step, so that when the circuit is stable, the digital output of the ADC unit does not vary with the analog input, so as to stabilize the system. In other words, the system is an open loop system at this time. Mixed-signal control apparatuses for conventional modulation systems are required to satisfy equation (1) as follows.qADC>G0qDAC  (1),in which G0 represents a control to output gain, i.e., a transfer function of the modulation system.
When the modulation system is exemplified as a power device, the controlled variable can be an output voltage of the power device, the mixed-signal control apparatus can be a digitally controlled PWM apparatus, and the DAC unit can be a digital pulse width modulation (DPWM) unit. Generally, a quantization step qADC of a ADC unit and a quantization step of the DPWM unit qDPWM in digitally controlled PWM satisfy equation (2) as follows.G0qDPWM<αqADC  (2),in which α is a constant.
When a small G0 is selected, the limit cycle can be avoided. However, this unfortunately means a slow response. Further, in order to avoid the limit cycle, the qDPWM l (or qDAC) should be designed to have a very small value. However, this means the resolution of the DPWM unit (or the DAC unit) is higher than the resolution of the ADC unit by 2 bits more than usually suggested. For example, if the resolution of the ADC unit is 8 bits, then the resolution of the DAC unit is 10 bits. As shown in FIG. 2, when the resolution of the ADC unit is higher than the resolution of the DAC unit, it means that the quantization step qDAC of the DAC unit must be smaller than the quantization step qADC for satisfying equation (1).
Further, there will be a trade off between to satisfy equation (1) and to achieve a lower power design. When the designer intends to achieve a lower power by increasing qADC, he may also obtain a larger variation range of the output voltage Vo. As shown in FIG. 2, the output voltage Vo can be anywhere of a qADC. According to an assumption that qADC=100 mV, the output voltage Vo has a variation range of 100 mV, but the digital output of the ADC unit remains unchanged.
Furthermore, in view of the requirement of satisfying equation (1), when the designer intends to increase the response speed by increasing G0, he has to reduce qDAC at the same time, so as to increase the resolution of the DAC unit (i.e., increase the bit number of the DAC unit). However, it is a challenge for digital ICs to increase the resolution of the DAC units, because many problems and design complexity will be caused by increasing DAC clock speed. For example, with respect to DPWM design, if it has a resolution of 10 bits (e.g., the resolution of the ADC unit is 9 bits), and a switching frequency fsw of the power device to be designed is 1 MHz (i.e., having a period of 1 μs), then a corresponding time of each LSB is 1 μs/210=1 μs/1024=977 ps. In order to achieve such speed, the operation frequency of the DPWM unit must be as high as 1/(977 ps)=1.024 GHz.
In U.S. Pat. No. 7,301,488, Leung discloses that Silicon Laboratories Inc. resolves the issue of the limit cycle based on equation (1) or equation (2). Leung further proposes to achieve a digital PWM unit having a relatively high resolution by employing a programmable dither technique. However, since the issue of limit cycle is resolved based on equation (1) or equation (2), a controller, a filter, and a programmable dither control are required for complying with an adaptive adjustment.